‘RISC-V is Inevitable.’ Foundation Chairman Touts the Growingly Advantageous Position of the Open ISA
Authors: Thomas Sorensen and Earl Joseph
Publication Date: December 2022
Length: 5 pages
During the recent SC22 event in Dallas, Texas, RISC-V Foundation Chairman Professor Krste
Asanović from the EECS Department at UC, Berkeley gave a presentation detailing the technological and market position of RISC-V and its potential to become a leading ISA, supplanting the slate of proprietary ISAs that currently dominate the sector. According to Asanović, it is only a matter of time before the RISC-V instruction set architecture claims its rightful place in the HPC stack among other industry standards like Ethernet, Posix, or SQL.
HPC Supplants Smart Phones as Key Business Driver at World’s Largest Chip Foundry
Steve Conway, Bob Sorensen, Alex Norton, and Earl Joseph
Taiwan-based TSMC, the world's largest chip foundry, recently announced (https://www.eetimes.com/document.asp?doc_id=1332869) that high performance computing (HPC) has supplanted smart phones as the most important driver of its business, although presumably not yet the largest financially.
January 2018 | Quick Take
Updated HPC Market Forecast Compared To Previous Forecast
Earl Joseph, Steve Conway and Alex Norton
This Quick Take presents the new Hyperion Research forecast compared to the previous (May 2018) five-year HPC forecast. The HPC market grew faster than expected in 2018 at 15.6% growth over 2017, resulting in sales of $14.5 billion for the year.
May 2019 | Quick Take