Japan, US Renew Commitment to Economic Order in CHIPS Era
Authors: Tom Sorensen, Bob Sorensen
Publication Date: 9 2022
Length: 1 pages
During an inaugural ministerial meeting of the U.S.-Japan Economic Policy Consultative Committee (EPCC) in July, a joint statement was presented detailing a renewed and explicit commitment to regional economic stability, fairness, and hardiness. The statement, which includes an action plan, enumerates four main goals: realizing peace and prosperity through rules-based economic order, countering economic coercion and unfair opaque lending practices, promoting and securing critical and emerging technologies and critical infrastructure, and strengthening supply chain resilience. While renewed and steady efforts to maintain regional welfare are an end within themselves, this joint statement takes on an additional layer of complexity and purpose when considered in light of the recent U.S. CHIPS Act, a semiconductor promotion policy whose U.S.-only tone has the potential to cause regional turbulence and heighten international trade tensions.
A Look at the EU’s Four Pillar Strategy for Leadership in HPC
Mark Nossokoff, Steve Conway, Earl Joseph
High performance computers (HPCs) are recognized globally as fundamental tools for conducting R&D, innovation and advancing the economic competitiveness of nations. More countries than ever are increasing their spending on HPC infrastructure and critical associated areas such as AI, cloud, quantum computing, applications development and optimization, and workforce development and retention. The European Commission (EC), through the EuroHPC Joint Undertaking (JU), Digital Europe Programme (DEP), and Horizon 2020/Europe funding programs, fully recognized this criticality for the European Union (EU) to fortify its global HPC leadership position. Further refining and extending its initial long-term mission, the JU has instituted a Four Pillar Strategy focusing on Infrastructure, Technologies, Applications, and Take-Up and Skill Sets, to define an approach to help realize its HPC ambitions. Continued execution of this strategy should well-position the EU to achieve its goals of deploying an integrated world-class supercomputing and data infrastructure.
September 20 | Uncategorized
World’s First Data Center APU Stood Up in AMD Laboratory
Tom Sorensen and Alex Norton
During the recent Wells Fargo 2022 TMT Summit, Mark Papermaster, CTO of AMD, reported that the Instinct MI300 accelerated processing unit (APU) is, as of early December 2022, up and running. Currently confined to their in-house lab, the Instinct MI300 will be used in the exascale supercomputer currently in development at Lawrence Livermore National Laboratory, El Capitan, scheduled to be delivered in 2024. Described by Papermaster as a "true datacenter APU," AMD expects general availability of the processor in 2023. This multi-chiplet processor makes use of both AMD's Zen 4 (x86) CPU architecture and CDNA 3, AMD's GPU architecture, designed specifically with exascale computing in mind, and will be produced by Taiwan's TSCM at the 5nm process node. Papermaster sees this development as an important way to continue introducing greater density and optimization into components now that the sector is no longer in the era of the "old Moore's Law."
December 2022 | Uncategorized