HPC Users Express Mixed Optimism Towards Adopting Edge Computing

In a signed agreement published in December of 2022, the EuroHPC Joint Undertaking (EuroHPC JU) called for proposals to fund a €270M effort to develop a European HPC infrastructure built on the RISC-V open ecosystem. The effort also includes fostering an overall open-source RISC-V community, code porting capabilities, and the development of chiplets based on the RISC-V open instruction set architecture (ISA). RISC-V stands apart from other ISAs as an open-standard that is free to license and has no IP requirements. RISC-V currently has a few offerings in the base product but has clear potential in meeting flexibility and customizability needs over proprietary chip counterparts.

During the recent Wells Fargo 2022 TMT Summit, Mark Papermaster, CTO of AMD, reported that the Instinct MI300 accelerated processing unit (APU) is, as of early December 2022, up and running. Currently confined to their in-house lab, the Instinct MI300 will be used in the exascale supercomputer currently in development at Lawrence Livermore National Laboratory, El Capitan, scheduled to be delivered in 2024. Described by Papermaster as a "true datacenter APU," AMD expects general availability of the processor in 2023. This multi-chiplet processor makes use of both AMD's Zen 4 (x86) CPU architecture and CDNA 3, AMD's GPU architecture, designed specifically with exascale computing in mind, and will be produced by Taiwan's TSCM at the 5nm process node. Papermaster sees this development as an important way to continue introducing greater density and optimization into components now that the sector is no longer in the era of the "old Moore's Law."