TESTING

During an inaugural ministerial meeting of the U.S.-Japan Economic Policy Consultative Committee (EPCC) in July, a joint statement was presented detailing a renewed and explicit commitment to regional economic stability, fairness, and hardiness. The statement, which includes an action plan, enumerates four main goals: realizing peace and prosperity through rules-based economic order, countering economic coercion and unfair opaque lending practices, promoting and securing critical and emerging technologies and critical infrastructure, and strengthening supply chain resilience. While renewed and steady efforts to maintain regional welfare are an end within themselves, this joint statement takes on an additional layer of complexity and purpose when considered in light of the recent U.S. CHIPS Act, a semiconductor promotion policy whose U.S.-only tone has the potential to cause regional turbulence and heighten international trade tensions.

In a signed agreement published in December of 2022, the EuroHPC Joint Undertaking (EuroHPC JU) called for proposals to fund a €270M effort to develop a European HPC infrastructure built on the RISC-V open ecosystem. The effort also includes fostering an overall open-source RISC-V community, code porting capabilities, and the development of chiplets based on the RISC-V open instruction set architecture (ISA). RISC-V stands apart from other ISAs as an open-standard that is free to license and has no IP requirements. RISC-V currently has a few offerings in the base product but has clear potential in meeting flexibility and customizability needs over proprietary chip counterparts.